1. Field of the Invention
The present disclosure relates to a readout circuit, a solid-state imaging apparatus, and a method for driving a readout circuit.
2. Description of the Related Art
A CMOS image sensor and a CCD image sensor include a pixel which includes a photoelectric conversion element, and a peripheral circuit which includes a readout circuit for reading out a signal that has been generated by photoelectric conversion in the pixel. In particular, CMOS image sensors are becoming to have higher functionalities due to having various modes. For instance, there is a CMOS image sensor which can switch resolution or a read out speed. As for image sensors associated with the above, there is a CMOS image sensor in which an input voltage range of the readout circuit changes and an order of input voltages change, according to the modes.
In Japanese Patent Application Laid-Open No. 2010-74784, a solid-state imaging apparatus is described which includes a photoelectric conversion element, a resetting element for resetting the photoelectric conversion element, and a plurality of clamping capacitors for accumulating electric charges therein which have been generated in the photoelectric conversion element and then have been amplified by an amplifier unit. The solid-state imaging apparatus further includes common nodes which are provided on each of the clamping capacitors and can be connected to the clamping capacitor, a plurality of pixel selecting switches each connected between the clamping capacitor and the common node, and a clamping unit for fixing the common node to a reference voltage. The solid-state imaging apparatus further includes a sampling and holding circuit which is connected to the common node through the clamping unit, and samples and holds electric charges according to the electric charge of the common node. In a first mode, the solid-state imaging apparatus accumulates the output of the amplifier unit according to the amount of an electric charge which has been obtained through photoelectric conversion by the photoelectric conversion element, in the clamping capacitor as a photo signal, and then after the photoelectric conversion element has been reset by a resetting element, accumulates the signal to be output in response to the reset by the amplifier unit, in the clamping capacitor as a reset signal. In a second mode, after the photoelectric conversion element has been reset by the resetting element, the solid-state imaging apparatus accumulates the signal to be output in response to the reset by the amplifier unit, in the clamping capacitor as the reset signal. Next, the solid-state imaging apparatus accumulates the output of the amplifier unit according to the amount of the electric charges which has been obtained through the photoelectric conversion by the photoelectric conversion element in the clamping capacitor as the photo signal to sample and hold the reset signal and a difference between the photo signal and the reset signal.
In the configuration described in Japanese Patent Application Laid-Open No. 2010-74784, in the first mode, the reset signal is input into the clamping capacitor after the photo signal, and in the second mode, the photo signal is input into the clamping capacitor after the reset signal. Accordingly, the potentials which appear in the output of the clamping unit are also different. In the first mode, the output potential of the clamping unit when the photo signal has been input into the clamping unit shall be represented by an output potential 1, and the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 2. In addition, in the second mode, the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 3, and the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 4. Then, the relationship of the magnitude between the output potential 1 and the output potential 2 and the relationship of the magnitude between the output potential 3 and the output potential 4 are reversed. The output potential 2 of the clamping unit in the first mode and the output potential 4 of the clamping unit in the second mode becomes an electric signal which shows the difference between the photo signal and the reset signal, and the magnitude, or the polarity of the output potential 2 and the output potential 4, is reversed.
In this case, even when a dynamic range in which the clamping unit is operated is appropriate in the first mode, the dynamic range becomes narrow in the second mode, and a sufficient dynamic range may not be available. In Japanese Patent Application Laid-Open No. 2010-74784, it is described in FIG. 7 and the second embodiment that reference voltages VC0R1 and VC0R2 to be input into the clamping unit are changed according to the mode, and thereby the dynamic range is appropriately secured. However, in the embodiment, such a case is considered that even when the reference potential VC0R1 or VC0R2 to be input into an amplifier 201 is selected and used so as to suit the mode, the dynamic range cannot still be secured depending on the configuration of an amplifier constituting the clamping unit.